Method and apparatus with channel stop doped devices
AssigneeSynopsys, Inc.
InventorVictor Moroz
Life of this patent
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Abstract
Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
Claims23
A method of performing channel stop doping in an integrated circuit, comprising:
- implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
- making undoped semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants;
- and
- making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
A nontransitory computer readable medium with computer executable instructions determining a layout of an integrated circuit design, the computer executable instructions including:
- first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
- and
- second computer executable instructions defining second layout locations making a transistor with a transistor channel in undoped semiconductor material, the undoped semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
A set of lithographic masks determining a layout of an integrated circuit design, including:
- a first lithographic mask defining first layout locations for implanting a first part of a surface of a semiconductor substrate with dopants and a second part of the surface with p-type dopants;
- and
- a second lithographic mask defining second layout locations making a transistor with a transistor channel in undoped semiconductor material, the undoped semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
A computer system for laying out an integrated circuit design, the computer system comprising a processor and a memory,
- the computer system generating a layout of the integrated circuit design, the layout defining a plurality of masks, the computer system configured to perform computer executable instructions comprising:
- first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
- and
- second computer executable instructions defining second layout locations making a transistor with a transistor channel in undoped semiconductor material, the undoped semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.
Dependencies are inferred from the claim text.