Inter-integrated circuit-slave interface, and method for operating an inter-integrated circuit-slave interface
AssigneeRobert Bosch GmbH
InventorDorde CVEJANOVIC
Life of this patent
Estimating the term…
Abstract
An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.
Claims11
An inter-integrated circuit slave interface, comprising:
- a data line;
- and
- a clock line, the clock line having a first input buffer and the data line having a second input buffer and an output buffer, the data line for transmission of a data input signal and a data output signal, and the clock line for the transmission of a clock signal, wherein the clock line has a first delay element, and the data line has a second delay element and a third delay element, the first delay element being configured to delay an ascending flank of the clock signal by a first time and a descending flank of the clock signal by a second time, the second delay element being configured to delay an ascending flank of the data input signal by a third time and a descending flank of the data input signal by a fourth time, and the third delay element being configured to delay an ascending flank of the data output signal by a fifth time and a descending flank of the data output signal by a sixth time.
An application-specific integrated circuit, comprising:
- an inter-integrated circuit slave interface including a data line, and a clock line, the clock line having a first input buffer and the data line having a second input buffer and an output buffer, the data line for transmission of a data input signal and a data output signal, and the clock line for the transmission of a clock signal, wherein the clock line has a first delay element, and the data line has a second delay element and a third delay element, the first delay element being configured to delay an ascending flank of the clock signal by a first time and a descending flank of the clock signal by a second time, the second delay element being configured to delay an ascending flank of the data input signal by a third time and a descending flank of the data input signal by a fourth time, and the third delay element being configured to delay an ascending flank of the data output signal by a fifth time and a descending flank of the data output signal by a sixth time.
A method for operating an inter-integrated circuit slave interface having a data line and a clock line, the clock line having a first input buffer and the data line having a second input buffer and an output buffer, the data line for transmission of a data input signal and a data output signal, the clock line for transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element, the method comprising:
- delaying an ascending flank of the clock signal by a first time;
- delaying a descending flank of the clock signal by a second time;
- delaying an ascending flank of a data input signal by a third time;
- delaying a descending flank of a data input signal by a fourth time;
- delaying an ascending flank of a data output signal by a fifth time;
- and
- delaying a descending flank of a data output signal by a sixth time.
Dependencies are inferred from the claim text.