Multilane serdes clock and data skew alignment for multi-standard support

A communication system, comprising:

• a first communication channel that includes
• a first phase interpolator configured to receive a first master clock signal and generates a first phase adjusted clock signal,
• a first divider configured to divide the first phase adjusted clock signal by a first factor to generate a first divided clock signal, the first divided clock signal configured to clock a first data stream through the first communication channel, and
• a second divider configured to divide the first divided clock signal to generate a second divided clock signal;
• a second communication channel that includes
• a second phase interpolator configured to receive a second master clock signal and generate a second phase adjusted clock signal,
• a third divider configured to divide the second phase adjusted clock signal by a second factor that is different than the first factor to generate a third divided clock signal, the third divided clock signal configured to clock a second data stream through the second communication channel, and
• a fourth divider configured to divide the third divided clock signal to generate a fourth divided clock signal of a same frequency as the second divided clock signal;
• and
• a phase detector configured to determine a phase difference between the second divided clock signal and the fourth divided clock signal;
• wherein a phase of the second phase adjusted clock signal is adjusted by the second phase interpolator based on the determined phase difference.

A method, comprising:

• generating a first phase adjusted clock signal for a first communication channel based on a master clock signal;
• generating a first divided clock signal based on the first phase adjusted clock signal;
• generating a second phase adjusted clock signal for a second communication channel based on the master clock signal;
• generating a second divided clock signal based on the second phase adjusted clock signal;
• determining a first phase difference between the first divided clock signal and the second divided clock signal;
• adjusting a phase of the second phase adjusted clock signal based on the first determined phase difference.