US 2014/0153575 A1 · PACKET DATA PROCESSOR IN A COMMUNICATIONS PROCESSOR ARCHITECTURE

Abstract

Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be pre-fetched into local instruction memory (e.g., local instruction cache). The flow identification might be used to select different portions of the packet and different software to be pre-fetched.

Claims20

Dependent claims

A network processor comprising:

a shared memory;
an input/output module configured to receive a packet and store the received packet in the shared memory;
a packet processing module;
and
a processor core module having a local memory;
wherein the packet processing module is configured to:
classify the received packet stored in the shared memory,
identify which one of one or more of a known flow the received packet pertains,
retrieve structural metadata corresponding to the identified flow of the received packet, and
pass to the processor core module the structural metadata;
and
wherein the processor core module is configured to:
pre-fetch content at address locations in the shared memory specified by the structural metadata,
store the pre-fetched content into the local memory, and
process the pre-fetched content stored in the local memory.

12 more elements

Dependencies are inferred from the claim text.

Packet data processor in a communications processor architecture

Life of this patent

Packet data processor in a communications processor architecture

Life of this patent

Abstract

Claims20