Simultaneous Two/Dual Port Access on 6T SRAM

A method comprising:

• triggering generation of a first internal clock signal from a clock signal, wherein a first internal clock signal edge and a second internal clock edge of the first internal clock signal are generated from an edge of the clock signal, and wherein the second internal clock edge has a direction opposite to a direction of the first internal clock signal edge, and wherein the second internal clock edge is immediately after the first internal clock signal edge, with no other edges therebetween;
• triggering generation of a second internal clock signal, wherein a third internal clock signal edge of the second internal clock signal is generated from the second internal clock edge of the first internal clock signal;
• and
• triggering a write operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array using the third internal clock signal edge.

A device comprising:

• a read/write clock generator comprising an input, a first output, and a second output, wherein the read/write clock generator is configured to generate from an edge of a clock signal received from the input, and output a first internal clock signal and a second internal clock signal to the first output and the second output, respectively;
• a read pre-decoder comprising a first input connected to the first output of the read/write clock generator, wherein the read pre-decoder is configured to, upon the first internal clock signal, pre-decoding a row/column address of a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array;
• a write pre-decoder comprising a second input connected to the second output of the read/write clock generator, wherein the write pre-decoder is configured to, upon the second internal clock signal, pre-decoding the row/column address of the 6T SRAM cell;
• and
• a read/write row/column decoder connected to an output of the read pre-decoder and an output of the write pre-decoder, wherein the read/write row decoder is configured to select a word-line of the SRAM array and read/write column decoder is configured to select a active column of SRAM array using addresses decoded by the read pre-decoder and the write pre-decoder.