Read Assist Scheme for Reducing Read Access Time in a Memory

A memory circuit, comprising:

• a plurality of memory cells;
• at least one word line and a plurality of bit lines, the word line and bit lines being coupled with the memory cells for selectively accessing the memory cells;
• at least one sense circuit operative to read data stored in a selected one of the memory cells;
• a controller operative to receive, as input control signals, an address signal and a data signal, and to generate a plurality of output control signals for accessing one or more of the plurality of memory cells as a function of the input control signals;
• and
• a read circuit, the read circuit comprising:
• a precharge circuit coupled with at least a subset of the bit lines and the sense circuit, the precharge circuit being operative to receive at least a first control signal, and being operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level;
• and
• a transmission gate operative to selectively connect a given one of the bit lines with the sense circuit during a second mode as a function of at least a second control signal, the second control signal being a delayed version of the first control signal, such that when reading a first logic level from the selected one of the memory cells, when the input of the sense circuit is connected with the given one of the bit lines, the given one of the bit lines is discharged to at least a third voltage, the third voltage being between the first and second voltage levels, thereby reducing a read access time in the memory circuit.