SRAM Cell Comprising FinFETs

A Static Random Access Memory (SRAM) cell comprising:

• a p-well region;
• a first and a second n-well region on opposite sides of the p-well region;
• a CVss line carrying a VSS power supply voltage over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region;
• a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively;
• a first pull-down FinFET and a second pull-down FinFET in the p-well region;
• and
• a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively.

A Static Random Access Memory (SRAM) cell comprising:

• a p-well region;
• a first n-well region and a second n-well region on opposite sides of the p-well region;
• a long boundary and a short boundary, with the short boundary shorter than the long boundary;
• a CVss line carrying a VSS power supply voltage overlapping the p-well region, wherein the CVss line is parallel to the short boundary;
• a bit-line and a bit-line bar on opposite sides of the CVss line, wherein the bit-line and the bit-line bar are configured to carry complementary bit-line signals, and wherein the bit-line and the bit-line bar overlap the first n-well region and the second n-well region, respectively;
• a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET in the first n-well region and the second n-well region, respectively;
• a first pull-down FinFET and a second pull-down FinFET in the p-well region;
• and
• a first pass-gate FinFET and a second pass-gate FinFET in the first n-well region and the second n-well region, respectively.