Semiconductor storage device

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
• and
• a plurality of memory cell power supply circuits each configured to supply a same memory cell power supply to a subset of the plurality of memory cells which is connected to a same bit line,
• wherein
• the plurality of memory cell power supply circuits each include a first and a second PMOS transistor connected together in series between a first and a second power supply,
• a connection point between the first and second PMOS transistors is output as the memory cell power supply,
• a control signal which is based on a write control signal, but not based on a column select signal, is input to a gate terminal of the first PMOS transistor, and
• a control signal which is based on the column select signal and the write control signal is input to a gate terminal of the second PMOS transistor.

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
• and
• a plurality of memory cell power supply circuits each configured to supply a same memory cell power supply to a subset of the plurality of memory cells which is connected to a same bit line,
• wherein
• the plurality of memory cell power supply circuits each include a first and a second PMOS transistor connected together in series between a first and a second power supply,
• a connection point between the first and second PMOS transistors is output as the memory cell power supply,
• a control signal which is based on a column select signal and a write control signal, is input to a gate terminal of the first PMOS transistor,
• a logically inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor, and
• the absolute value of the threshold voltage of the second PMOS transistor is set to be larger than the absolute values of the threshold voltages of a load transistor and a drive transistor of the memory cell.

A semiconductor storage device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
• and
• a plurality of memory cell power supply circuits each configured to supply a same memory cell power supply to a subset of the plurality of memory cells which is connected to a same bit line,
• wherein
• the plurality of memory cell power supply circuits each have a function of causing, during write operation, the potential of the memory cell power supply to be lower than the potential of the first power supply, and
• the semiconductor storage device further includes
• a leakage current compensation circuit including a MOS transistor connected between the first power supply and the memory cell power supply, and configured to compensate for a leakage current of the memory cell power supply while the potential of the memory cell power supply is caused to be lower than the potential of the first power supply.