Semiconductor memory apparatus, refresh method and system

Abstract

Disclosed are a semiconductor memory apparatus, and refresh method and system. The semiconductor memory apparatus includes: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells. Therefore, the refresh of the resistive memory is efficiently performed, and as a result, performance deterioration may be minimized, and a lifespan of the device may be extended.

Dependencies are inferred from the claim text.