Semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorTsuneo Inaba
Life of this patent
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Abstract
A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
Claims16
A semiconductor storage device comprising:
- a semiconductor substrate;
- a plurality of memory cells on an upper portion of or above the semiconductor substrate, the memory cells including storage elements storing therein data and switching elements;
- a plurality of active areas, on which the switching elements of the memory cells are respectively formed, isolated from one another to correspond to the memory cells, respectively, and arranged on the semiconductor substrate in a first direction, the active areas adjacent in a second direction substantially orthogonal to the first direction being arranged to be half-pitch-staggered in the first direction;
- and
- a plurality of upper electrodes each connecting one end of the storage element of a first memory cell to the switching element of a second memory cell adjacent to the first memory cell in the second direction and to a bit line, the first and second memory cells being among the plurality of memory cells.
A semiconductor storage device comprising:
- a plurality of bit lines;
- a plurality of word lines;
- and
- a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines, each gate node of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines being respectively connected to different ones of the word lines, wherein
- a plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
Dependencies are inferred from the claim text.