Shift register and flat panel display device including the same

A flat panel display device comprising:

• a display panel configured to comprise an active area, comprising a plurality of pixels that are respectively formed in a plurality of pixel areas defined by intersections between a plurality of gate lines and a plurality of data lines, and an inactive area defined near the active area;
• a plurality of data drivers configured to convert input pixel data into data signals, and respectively supply the data signals to the plurality of data lines;
• a gate driver provided in the inactive area of the display panel in connection with the plurality of gate lines, and configured to generate a gate-on voltage pulse on the basis of a gate start signal and a plurality of clock signals to supply the gate-on voltage pulse to the plurality of gate lines;
• and
• a timing controller configured to convert input video data into the pixel data, supply the pixel data to the plurality of data drivers, and supply a gate control signal, comprising the gate start signal and the plurality of clock signals, to the gate driver,
• wherein the gate driver includes a shift register comprising:
• a pull-up transistor configured to supply one of the plurality of clock signals to an output node according to a voltage of a first node;
• a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node;
• a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal;
• and
• a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines by using the clock signal supplied to the output node, respectively.