Time Interleaving Analog-to-Digital Converter

A method for operating a time interleaving Analog-to-Digital Converter (ADC), said time interleaving Analog-to-Digital Converter comprising:

• a plurality of ADCs;
• a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs;
• and
• a timing adjustment circuit;
• said method comprising, with said timing adjustment circuit:
• receiving and adjusting the clock signals before the clock signals are received by the plurality of ADCs;
• and
• adjusting a bandwidth of the plurality of ADCs.

A time interleaving Analog-to-Digital Converter (ADC), comprising:

• a plurality of ADCs;
• a timing generator which generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs;
• and
• a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate and time adjustment values;
• in which the timing adjustment includes time increments smaller than smallest delay created by the clock adjustment circuitry when applied to the ADC.