Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (ic) chip including the circuit and method of switching voltage on chip

A method of configuring on-chip supply voltage being supplied to one or more chip circuits, said method comprising:

• selecting a first voltage supply mode;
• floating one side of a first capacitor in a pair of series connected capacitors, the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair;
• and while said first voltage supply mode is selected,
• asserting a first clock;
• coupling said first side of said second capacitor to a first voltage supply line responsive to said first clock;
• coupling the other side of said second capacitor to an on-chip supply voltage output (Vout)responsive to said first clock;
• asserting a second clock, said first clock and said second clock not overlapping;
• coupling said first side of said second capacitor to said on-chip supply voltage output responsive to said second clock;
• coupling the other side of said second capacitor to a second voltage supply line responsive to said second clock;
• and
• returning to assert said first clock.

A method of configuring on-chip supply voltage being supplied to one or more CMOS chip circuits, said method comprising:

• selecting a first voltage supply mode;
• floating one side of a first capacitor in a pair of series connected capacitors connected to a field effect transistor (FET) totem connected between a first supply (V1) and a second supply (V2), the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair, said one side being connected between a first PFET and NFET (PN FET) totem pair, said other side and said first side being connected between a second PN FET totem pair and the opposite side of said second capacitor being connected between a third PN FET totem pair;
• alternately turning PFETs off and on and NFETs on and off in the second and third PN FET totem pair, said second and third PN FET totem pairs alternately switching opposite sides of said second capacitor to a voltage supply output (Vout);
• selecting a second voltage supply mode;
• alternately turning PFETs off and on and NFETs on and off in the first, second and third PN FET totem pairs, said first PN FET totem pair alternately floating and coupling said one side of said first capacitor to V1, and said second and third PN FET totem pairs simultaneously alternately switching said other side of said second capacitor to Vout when said one side is floating, said second and third PN FET totem pairs alternately switching opposite sides of said second capacitor to Vout;
• and
• waiting to reselect said first voltage supply mode.

A method of configuring on-chip supply voltage being supplied to one or more CMOS chip circuits, said method comprising:

• asserting a configuration select in a first state, said first state selecting a first voltage supply mode;
• turning a shunting field effect transistor (FET) on, said shunting FET shorting a first PFET and NFET pair (PN FET pair) in a FET totem connected between a first supply voltage (V1) and a second supply voltage (V2), one side of a first capacitor in a pair of series connected capacitors connected between the PFET and NFET in said first PN FET pair;
• blocking a PFET clock and an NFET clock to said first PN FET pair, both the PFET and NFET in said first PN FET pair being held off, said one side of said first capacitor floating;
• switching on PFETs in said the second and third PN FET totem pair in a first half cycle, said PFET in said second PN FET totem pair switching said first side of said second capacitor to V1, and said PFET in said third PN FET totem pair switching the opposite side of said second capacitor to Vout, the corresponding NFETs in both pair being off;
• switching said PFETs off in a second half cycle and NFETs on, on NFETs switching said first side of said second capacitor to Vout and said other side of said second capacitor to V2;
• returning to switching on PFETs until said configuration select is asserted in a second state, and when asserted in said second state a second voltage supply mode has been selected;
• and then
• turning off said shunting FET;
• passing said PFET clock and said NFET clock to said first PN FET pair, both the PFET and NFET in said first PN FET pair being gated on by a respective clock;
• switching on PFETs in the first, second and third PN FET totem pairs in a first half cycle, said PFET in said first PN FET totem pair switching said one side of said first capacitor to V1, and said PFET in said third PN FET totem pair switching the opposite side of said second capacitor to Vout, the corresponding NFETs in said first, second and third PN FET totem pairs being off;
• switching said PFETs off in a second half cycle and NFETs on, on NFETs switching said first side of said second capacitor to Vout and said other side of said second capacitor to V1;
• and
• returning to switching on PFETs in all three PN FET totem pairs until said first voltage supply mode is reselected.