Capacitor, charge pump circuit, and semiconductor device
AssigneeRenesas Electronics Corporation
InventorsToshio FUJIMOTO, Takashi ITO
Life of this patent
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Abstract
There is provided a capacitor with a reduced layout area. A capacitor has an electrode EL1 formed by using a first polysilicon layer, an electrode EL2 formed by using a second polysilicon layer over the first polysilicon layer, and electrodes EL3 to EL6 formed by using second through fifth metal wiring layers over the second polysilicon layer. An N-type well and the electrode EL1 make up a capacitor element 11, the electrodes EL1, EL2 make up a capacitor element 12, and the electrodes EL3 to EL6 make up a capacitor element 13. The capacitor elements 11 to 13 are coupled in parallel between terminals T1, T2.
Claims16
A capacitor comprising:
- a first electrode formed by using a first polysilicon layer over a semiconductor substrate;
- a second electrode formed by using a second polysilicon layer over the first polysilicon layer;
- and
- third and fourth electrodes formed by using a metal wiring layer over the second polysilicon layer,
- wherein the semiconductor substrate and the first electrode are provided facing each other and make up a first capacitor element;
- wherein the first and second electrodes are provided facing each other and make up a second capacitor element, and
- wherein the third and fourth electrodes are provided side by side and make up a third capacitor element.
The capacitor according to claim. 1, further comprising first and second terminals,
- wherein the first and second capacitor elements are coupled in series or in parallel, and
- wherein the third capacitor element as well as the first and second capacitor elements is coupled between the first and second terminals.
A semiconductor device comprising:
- a semiconductor substrate;
- and
- a charge pump circuit that is formed over the semiconductor substrate and boots a power supply voltage to a predetermined step-up voltage,
- the charge pump circuit comprising:
- N transistors for transferring electric charge (where N is an integer of 2 or more) coupled in series between a power supply voltage terminal and an output voltage terminal;
- and
- (N−1) step-up capacitors, each comprising a first terminal that receives a clock signal and a second terminal that is coupled to a series-coupling node between transistors for transferring electric charge,
- each of the step-up capacitors comprising:
- a layered capacitor having first and second polysilicon layers deposited with an insulation film in between over a well area of the semiconductor substrate, and
- a MIM capacitor placed just over the layered capacitor and formed by using a metal wiring layer above the second polysilicon layer.
Dependencies are inferred from the claim text.