Apparatus and methods for altering the timing of a clock signal

A method comprising:

• adjusting, at a first clock signal timing cell, a rising clock edge transition of an intermediate clock signal from a first voltage level to a second voltage level based at least in part on a first bias signal, the intermediate clock signal provided responsive to the input clock signal;
• and
• adjusting, at a second clock signal timing cell, a falling clock edge transition of an output clock signal from the second voltage level to the first voltage level based at least in part on a second bias signal, the output clock signal provided responsive to the intermediate clock signal.

An apparatus comprising:

• a first bias controlled clock timing cell configured to alter timing of a clock signal edge based on multi-bit signals, the first bias controlled clock timing cell including a bias controlled inverter coupled in parallel with an inverter having weaker drive strength than the bias controlled inverter;
• and
• a programmable controller configured to provide a multi-bit signal to the first bias controlled clock timing cell to control the bias controlled inverter.