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US 2014/0152359 A1Published application
Locked loop circuits and methods
AssigneeCambridge Silicon Radio Limited
InventorsDuncan Mcleod, Farshid Nowshadi, David Chappaz
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Abstract
The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.
Claims12
A locked loop circuit, comprising:
- a delay cell for receiving a clock signal, applying a delay in accordance with a saw-tooth pattern and outputting a delayed clock signal;
- a comparator for comparing the phase of the delayed clock signal and the phase of an output signal, and outputting a comparison signal;
- an integrator for integrating the comparison signal and outputting an integrated signal;
- an oscillator for generating the output signal as controlled by the integrated signal;
- and
- feedback circuitry for measuring the comparison signal at a wrap point of the saw-tooth pattern and controlling the amplitude of the saw-tooth pattern in dependence on the measured comparison signal.
3 more elements
Dependencies are inferred from the claim text.