Semiconductor apparatus and duty cycle correction method thereof

A semiconductor apparatus comprising:

• a duty cycle correction block configured to generate a duty corrected clock by correcting a duty cycle of an internal clock, to adjust a phase of a rising edge of the duty corrected clock when a delay locked loop is reset, and to adjust a phase of a falling edge of the duty corrected clock when the delay locked loop is locked;
• and
• the delay locked loop configured to receive an external clock to output the internal clock, and to delay the external clock by a variable delay amount to output the internal clock when adjustment of the phase of the rising edge of the duty corrected clock by the duty cycle correction block is completed.

A duty cycle correction method of a semiconductor apparatus, comprising:

• correcting a duty cycle by adjusting a phase of a first edge of a clock and generating a duty corrected clock;
• and
• performing a delay locking by delaying the duty corrected clock by a variable delay amount and generating a locked DLL clock.