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US 2014/0152357 A1Published application
Methods and circuits for reducing clock jitter
AssigneeRambus Inc.
InventorsJared Zerbe, Teva Stone, Jihong Ren
Life of this patent
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Abstract
A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
Claims30
An integrated circuit comprising:
- a data sampler having a data input node, a data output node, and a clock node;
- a data path extending to the data input node;
- a clock path extending from a clock source to the clock node and including a linear equalizer, the linear equalizer having an equalization control port;
- and
- equalization control circuitry coupled between the data output node and the equalization control port.
2 more elements
A sequential logic system comprising:
- a sequential storage element to capture a data signal on edges of a clock signal;
- a data path to communicate the data signal to the sequential storage element;
- a clock path to communicate the clock signal to the sequential storage element, the clock path including an equalizer to suppress high-frequency components relative to low-frequency components of the clock signal;
- and
- feedback circuitry between an output of the sequential storage element and the equalizer, the feedback circuitry to adjust the equalizer responsive to the captured data signal.
2 more elements
A method of timing receipt of a data signal, the method comprising:
- timing the data signal to a clock signal using a first sequential storage element;
- equalizing the clock signal, using an equalizer, to emphasize lower-frequency components of the clock signal relative to higher-frequency components of the clock signal;
- transmitting the data and the equalized clock signal to a second sequential storage element;
- sampling the data signal, using the second sequential storage element, on edges of the equalized clock signal;
- and
- adjusting the equalizing responsive to errors in the sampled data signal.
3 more elements
A communication system comprising:
- a data path to convey a data signal expressed as a series of symbols following a null period, the series of symbols including an initial symbol followed by subsequent symbols;
- a clock path having an equalizer to convey an equalized clock signal expressed as a series of clock edges following the null period, the clock edges including an initial clock edge followed by subsequent clock edges;
- and
- a data sampler having a data input node to receive the initial and subsequent symbols and a clock node to receive the initial and subsequent clock edges, the data sampler to sample the initial symbol using the initial clock edge.
1 more element
Dependencies are inferred from the claim text.