Sense-amplifier latch having single data input

Abstract

A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low.

Dependencies are inferred from the claim text.