US 2014/0152341 A1Published application

External component-less pvt compensation scheme for io buffers

AssigneeLSI Corporation

InventorAnuroop Iyengar

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Abstract

Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Claims20

Dependent claims

A method to provide Process-Voltage-Temperature (PVT) compensation for an Input/Output (IO) interface, said IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), said method comprising:

connecting said VBGR to a voltage reduction system;
reducing said VBGR by substantially half at said voltage reduction system to produce VBGR/2;
connecting said VBGR/2 to a current mirror system;
connecting said current mirror system to a high supply voltage (VDD);
connecting a driver bit cell to a low supply voltage (VSS);
connecting said current mirror system to said driver bit cell such that a process-variable-temperature current (IPVT) flows through said driver bit cell;
connecting said current mirror system to a compensated current controlled oscillator;
mirroring said IPVT at said current mirror system such that said compensated current controlled oscillator receives a control current (ICNTL) that is proportional to said IPVT;
generating an oscillation frequency (FOSC) at said compensated current controlled oscillator that is a function of said ICNTL;
connecting said FOSC to a digital system;
connecting said FREF to said digital system;
measuring, by said digital system, a desired count period based on FREF;
accumulating, by said digital system, a count of said FOSC at said digital system during said desired count period;
looking up, by said digital system, a PVT control bit value that correlates to said accumulated count of said FOSC in a look-up table containing a predetermined correlation of potential count values of said FOSC to desired PVT control bit values;
and
providing, by said digital system, said looked up PVT control bit value to said IO interface.

13 more elements

A Process-Voltage-Temperature (PVT) compensation system for an Input/Output (IO) interface, said IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), said PVT compensation system comprising:

a voltage reduction subsystem connected to said VBGR that reduces said VBGR by substantially half to produce VBGR/2;
a driver bit cell connected to a current mirror subsystem and to a low supply voltage (VSS);
said current mirror subsystem connected to said VBGR/2, to a high supply voltage (VDD), to said driver bit cell, and to a compensated current controlled oscillator such that a process-variable-temperature current (IPVT) flows through said driver bit cell and a mirrored control current (ICNTL) that is proportional to said IPVT is delivered to said compensated current controlled oscillator;
a compensated current controlled oscillator connected to said ICNTL that generates an oscillation frequency (FOSC) that is a function of said ICNTL;
a digital subsystem that is connected to said FOSC and to said FREF, and that measures a desired count period based on FREF, accumulates a count of said FOSC during said desired count period, looks up a PVT control bit value that correlates to said accumulated count of said FOSC in a look-up table containing a predetermined correlation of potential count values of said FOSC to desired PVT control bit values, and provides said looked up PVT control bit value to said IO interface in order for said IO interface to set a buffer impedance of said IO interface in accord with said looked up PVT control bit value.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/706,110Filed 5 Dec 2012
Published: 5 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 19/00369
Modifications for increasing the reliability for protection: modifications for compensating variations of temperature, supply voltage or other…
H03K 3/011
Details: modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03K 19/00346
Modifications for increasing the reliability for protection: modifications for eliminating interference or parasitic voltages or currents
H03K 19/00384
Modifications for compensating variations of temperature, supply voltage or other physical parameters: in field effect transistor circuits

Family

US 8,760,190 B1Related patent
US 2014/0152341 A1This patent

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