Semiconductor device

A semiconductor device comprising:

• a first flip-flop;
• a second flip-flop which is provided in a subsequent stage of the first flip-flop;
• and
• a malfunction pre-detecting circuit provided on a route branching off from a route to a data input terminal of the second flip-flop,
• the malfunction pre-detecting circuit comprising:
• a plurality of stages of delay elements coupled in series to delay input data that is input in parallel to the data input terminal of the second flip-flop;
• a plurality of third flip-flops, each receiving output of each delay element;
• a plurality of comparators, each comparing output of the second flip-flop and output of a third flip-flop linked thereto,
• wherein first test data and second test data are input to the malfunction pre-detecting circuit in an operation test mode for testing operation of the malfunction pre-detecting circuit and the second test data is input to a first stage of the stages of delay elements, and
• wherein the comparators each compare the first test data and output of the third flip-flop linked thereto in the operation test mode.