US 2014/0151900 A1 · STACKED PACKAGING USING RECONSTITUTED WAFERS

Abstract

An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Claims20

Dependent claims

A stacked package comprising:

a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer;
said top die and said bottom die being insulated from one another by an insulation arrangement;
said top die and said bottom die being interconnected through said insulation arrangement.

Dependencies are inferred from the claim text.

Facts

Application

14/175,985Filed 7 Feb 2014

Priority

14 Dec 2011

Published

5 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10W 90/00
Package configurations
H10P 54/00
Cutting or separating of wafers, substrates or parts of devices
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…

Stacked packaging using reconstituted wafers

Life of this patent

Stacked packaging using reconstituted wafers

Life of this patent

Abstract

Claims20