Semiconductor interconnect structures
AssigneeIntel Corporation
InventorsBoyan Boyanov, Kanwal Singh, James Clarke, Alan Myers
Life of this patent
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AssigneeIntel Corporation
InventorsBoyan Boyanov, Kanwal Singh, James Clarke, Alan Myers
Estimating the term…
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
A semiconductor device, comprising:
A multilayer integrated circuit device, comprising:
A method of forming a semiconductor device, comprising:
The method of claim er 18, further comprising depositing an additional insulator layer between the conformal etchstop layer and the second insulator structure.
Dependencies are inferred from the claim text.