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US 2014/0151877 A1Published application
Semiconductor package and method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHWAN-SIK LIM, Sunwon Kang, Jongho Lee
Life of this patent
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Abstract
A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.
Claims19
-10. (canceled)
A semiconductor package, comprising:
- a substrate having a plurality of first patterns disposed in a first direction, each of the plurality of first patterns including a first land and a first extension extending along a second direction that is substantially perpendicular to the first direction, wherein a first real bump is disposed on the first land and a plurality of first dummy bumps are disposed on the first extension;
- and
- a plurality of second patterns disposed in the first direction, each of the plurality of second patterns including a second land and a second extension, wherein a second real bump is disposed on the second land and a plurality of second dummy bumps are disposed on the second extension in the second direction,
- wherein the plurality of first patterns is a mirror image of the plurality of second patterns with respect to an imaginary center line extending in the first direction through the center of the substrate.
1 more element
A semiconductor package, comprising:
- a package substrate having a plurality of patterns, each comprising a land and an extension extending from the land in a first direction, wherein the land is configured to receive a conductive bump and the extension is configured to receive a plurality of dummy bumps spaced at an equal distance from each other, and wherein the plurality of patterns are positioned with a first set of patterns in a second direction perpendicular to the first direction, and a second set of patterns in the second direction, the first set of patterns and the second set of patterns opposing each other with respect to an imaginary line extending in the second direction along the center of the package substrate.
A semiconductor package, comprising:
- a package substrate;
- a semiconductor chip disposed on the package substrate, the semiconductor chip having a first bump group including a first real bump and a plurality of first dummy bumps and a second bump group including a second real bump and a plurality of second dummy bumps;
- a first pattern disposed on the package substrate and connected to the first bump group, the first pattern including a first land and a first extension, wherein the first real bump is disposed on the first land, and the plurality of first dummy bumps is disposed on the first extension;
- and
- a second pattern disposed on the substrate and connected to the second bump group, the second pattern including a second land and a second extension, wherein the second real bump is disposed on the second land, and the plurality of second dummy bumps is disposed on the second extension, and wherein the first pattern and the second pattern are spaced apart from each other and are disposed along a first line, and wherein the first pattern and the second pattern are substantially symmetrical with each other with respect to a center line between the first pattern and the second pattern, the center line substantially perpendicular with the first line.
2 more elements
Dependencies are inferred from the claim text.