Semiconductor package and process for fabricating same

A semiconductor package, comprising:

• a substrate, including:
• a dielectric layer having a plurality of openings;
• a conductive layer disposed adjacent to the dielectric layer;
• a plurality of conductive vias disposed in respective ones of the openings;
• and
• an etching stop layer disposed in the openings and contacting a top end of each of the plurality of conductive vias;
• wherein the conductive layer and the conductive vias are formed of the same material;
• a chip attached to a top side of the substrate and connected to the conductive layer;
• and
• a plurality of conductive bumps disposed adjacent to respective ones of the conductive vias,
• wherein the etching stop layer is connected to the conductive layer at a bottom surface of the conductive layer, and a bottom end of each conductive via is connected to the respective conductive bump such that the bottom end of the conductive via does not protrude from the respective opening.

A substrate, comprising:

• a dielectric layer having a plurality of openings with sidewalls extending between a first surface of the dielectric layer and a second surface of the dielectric layer;
• a conductive material disposed within the plurality of openings;
• a barrier layer disposed over the conductive material;
• a patterned conductive layer in physical contact with the dielectric layer, and in electrical contact with the conductive material through the barrier layer, wherein the patterned conductive layer is formed of the same material as the conductive material;
• and
• a solder resist layer disposed on the patterned conductive layer and exposing portions of the patterned conductive layer to form a plurality of contact pads.