Novel contact structure for a semiconductor device and methods of making same

A device, comprising:

• first and second spaced-apart active regions formed in a semiconducting substrate;
• a layer of gate insulation material positioned on said first active region;
• a first conductive line feature that has a first portion positioned above said layer of gate insulation material and a second portion that conductively contacts said second active region, said first conductive line feature having an end surface that is positioned above said second device region;
• a sidewall spacer formed on said end surface of said first conductive line feature;
• a doped source/drain region positioned in said second active region;
• and
• a contact doped region positioned in said second active region under said second portion of said first conductive line.

An SRAM device, comprising:

• first and second spaced-apart active regions formed in a semiconducting substrate;
• a first pull-up transistor formed in and above said first active region, said first pull-up transistor comprising a first gate insulation layer;
• a first conductive line feature comprised of at least one layer of conductive material, wherein a first portion of said first conductive line feature is positioned above said first gate insulation layer and a second portion of said first conductive line feature conductively contacts said second active region;
• a second pull-up transistor formed in and above said second active region, said second pull-up transistor comprising a second gate insulation layer;
• and
• a second conductive line feature comprised of at least one layer of conductive material, wherein a first portion of said second conductive line feature is positioned above said second gate insulation layer and a second portion of said second conductive line feature conductively contacts said first active region.

A method, comprising:

• forming first and second spaced-apart active regions in a semiconducting substrate;
• forming a layer of gate insulation material on at least said first and second active regions;
• performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region;
• and
• forming a conductive line feature that comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion that conductively contacts said exposed portion of said second active region.

A method, comprising:

• forming first and second spaced-apart active regions in a semiconducting substrate;
• forming a layer of gate insulation material on at least said first and second active regions;
• performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region;
• and
• performing an in situ doping deposition process to form a doped polysilicon conductive line feature that is doped with one of an N-type dopant or a P-type dopant, wherein said doped polysilicon conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion that conductively contacts said exposed portion of said second active region.

A method, comprising:

• forming first and second spaced-apart active regions in a semiconducting substrate;
• forming a layer of gate insulation material comprised of a high-k insulating material on at least said first and second active regions;
• performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region;
• and
• forming a conductive line feature comprised of at least one layer of metal, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said at least one layer of metal conductively contacts said exposed portion of said second active region.

A method, comprising:

• forming first and second spaced-apart active regions in a semiconducting substrate;
• forming a layer of gate insulation material comprised of a high-k insulating material on at least said first and second active regions;
• performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region;
• and
• forming a conductive line feature comprised of at least one layer of metal and a silicon-containing layer of material positioned above said at least one layer of metal, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said silicon-containing layer of material conductively contacts said exposed portion of said second active region.

A method, comprising:

• forming first and second spaced-apart active regions in a semiconducting substrate;
• forming a sacrificial gate structure above said first and second active regions;
• forming a sidewall spacer adjacent said sacrificial gate structure;
• removing said sacrificial gate structure to thereby define a gate cavity that is laterally defined by inner surfaces of said sidewall spacers;
• forming a layer of gate insulation material comprised of a high-k insulating material in said gate cavity on at least said first and second active regions;
• performing an etching process to remove a portion of said layer of gate insulation material formed on said second active region so as to thereby expose a portion of said second active region;
• and
• forming a conductive line feature comprised of at least one layer of metal within said cavity, wherein said conductive line feature comprises a first portion positioned above said layer of gate insulation material formed on said first active region and a second portion wherein said at least one layer of metal conductively contacts said exposed portion of said second active region.