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US 2014/0151792 A1Published application
High voltage high side dmos and the method for forming thereof
AssigneeMonolithic Power Systems, Inc.
InventorsJi-Young Yoo, Martin Garnett
Life of this patent
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Abstract
A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.
Claims16
A high voltage high side DMOS, comprising:
- a P-type substrate with an epitaxial layer formed on the P-type substrate;
- a field oxide formed on the epitaxial layer;
- an N-type well region formed in the epitaxial layer;
- a gate oxide formed on the epitaxial layer;
- a gate poly formed on the gate oxide and on the field oxide;
- a P-type base region formed in the epitaxial layer;
- a deep P-type region merging with the P-type base region formed in the epitaxial layer;
- an N-type lightly doped well region formed under the P-type base region in the epitaxial layer, wherein the N-type well region is formed in the N-type lightly doped well region;
- a first N-type highly doped region formed in the N-type well region;
- a second N-type highly doped region formed in the P-type base region;
- a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region;
- a TEOS layer formed on the gate poly;
- an inter layer dielectric formed on the TEOS layer and on the gate oxide;
- a drain electrode contacted with the first N-type highly doped region;
- and
- a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.
13 more elements
A method for forming a high voltage high side DMOS, comprising:
- forming an epitaxial layer on a substrate;
- forming a field oxide and an N-type well region in the epitaxial layer;
- forming a gate oxide on the epitaxial layer;
- forming a gate poly on the gate oxide and on the field oxide;
- forming a TEOS layer on the gate poly;
- forming a P-type base region in the epitaxial layer;
- forming a deep P-type region merging with the P-type base region in the epitaxial layer;
- forming a first N-type highly doped region in the N-type well region, forming a second N-type highly doped region and a P-type highly doped region adjacent to the second N-type highly doped region in the P-type base region;
- forming an inter layer dielectric on the TEOS layer and on the gate oxide;
- forming a drain electrode contacted with the first N-type highly doped region, and forming a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.
7 more elements
A high voltage high side DMOS, comprising:
- a P-type substrate with an epitaxial layer formed on the P-type substrate;
- a field oxide formed on the epitaxial layer;
- an N-type well region formed in the epitaxial layer;
- a gate oxide formed on the epitaxial layer;
- a gate poly formed on the gate oxide and on the field oxide;
- a P-type base region formed in the epitaxial layer;
- a first N-type highly doped region formed in the N-type well region;
- a second N-type highly doped region formed in the P-type base region;
- a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region;
- a TEOS layer formed on the gate poly;
- an inter layer dielectric formed on the TEOS layer and on the gate oxide;
- a drain electrode contacted with the first N-type highly doped region;
- and
- a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.
11 more elements
(canceled)
Dependencies are inferred from the claim text.