Nonvolatile memory including memory cell array having three-dimensional structure

A nonvolatile memory, comprising:

• a plurality of channel layers and a plurality of insulation layers that are alternately stacked on a substrate in a direction perpendicular to a major surface of the substrate, each of the plurality of channel layers including a plurality of channel films, and each of the plurality of channel layers disposed in a respective one of a plurality of planes that are parallel to the major surface of the substrate;
• a plurality of conductive materials that each extend downwardly from a top of the channel layers and the insulation layers in a direction perpendicular to the major surface of the substrate to at least partially cover at least one side surface of each channel film;
• a plurality of information storage films provided between the channel films of the channel layers and the conductive materials;
• and
• a plurality of bit lines connected to the channel layers, respectively,
• wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array,
• wherein the conductive materials are arranged as a first group including two or more conductive materials, a second group including two or more other conductive materials, and a third group including at least another conductive material that is between the first group and the second group, and
• wherein the nonvolatile memory is configured to erase the first group independent of the second group.

A nonvolatile memory, comprising:

• a stacked structure that includes a plurality of channel films and a plurality of insulation layers that are alternately stacked on a substrate in a direction perpendicular to a major surface of the substrate, wherein each of the plurality of channel films lies in a respective one of a plurality of planes that are parallel to the major surface of the substrate, and each of the plurality of channel films extending along a first direction;
• a plurality of conductive materials that each extend from a top of the stacked structure and along at least one side surface of the stacked structure to at least partially cover a respective side surface of each of the plurality of channel films;
• a plurality of information storage films provided between the channel films and the conductive materials;
• and
• a plurality of bit lines that are electrically connected to respective ones of the channel films,
• wherein the conductive materials, the information storage films, and the channel films are part of a three-dimensional memory cell array,
• wherein the conductive materials are arranged into at least first and second groups that are adjacent to each other, with each of the first and second groups including a plurality of adjacent ones of the conductive materials, and
• wherein a distance between the first group and the second group is greater than a distance between adjacent conductive materials in the first group.