Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency

A method comprising:

• forming a floating gate layer over a semiconductor substrate and a control gate layer over the floating gate layer;
• patterning the control gate layer, thereby forming a control gate having a first sidewall on a first side and a second sidewall on a second side;
• forming a first dielectric layer over the first sidewall and the second sidewall of the control gate;
• patterning the first dielectric layer along the first sidewall such that the first dielectric layer is discontinuous with the first dielectric layer along the second sidewall;
• after the patterning the first dielectric layer, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall;
• patterning the second dielectric layer along the first sidewall and the second sidewall, the second dielectric layer being in direct contact with the floating gate layer on the first side of the control gate;
• the first dielectric layer being interposed between the second dielectric layer and the floating gate layer on the second side of the control gate;
• patterning the floating gate layer using the first dielectric layer and the second dielectric layer as a mask, thereby forming a floating gate;
• removing the second dielectric layer along the first sidewall;
• and
• forming an erase gate along the first sidewall, the erase gate overlying at least a portion of the floating gate.

An apparatus comprising:

• a substrate;
• a floating gate over the substrate;
• a control gate over the floating gate, the floating gate having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;
• a first dielectric layer extending over a first sidewall and a second sidewall of the control gate, the first dielectric layer completely covering an upper surface of the second portion of the floating gate;
• and
• a second dielectric layer over the first dielectric layer, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate.