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US 2014/0151781 A1Published application
Process for fabricating a transistor comprising nanocrystals
AssigneeSTMicroelectronics (Roesset) SAS
InventorPHILIPPE BOIVIN
Life of this patent
Estimating the term…
Abstract
A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.
Claims24
1-15. (canceled)
A method for making a transistor comprising:
- forming source and drain regions in a substrate;
- forming a floating gate comprising a plurality of electrically conductive nanoparticles to accumulate electrical charge;
- deoxidizing a part of the floating gate adjacent the source region to define a space;
- and
- oxidizing the space to form an enlarged zone of an insulating layer adjacent the source region.
2 more elements
A method for making a transistor comprising:
- forming source and drain regions in a substrate;
- forming a floating gate comprising a plurality of electrically conductive nanoparticles to accumulate electrical charge;
- removing a part of the floating gate adjacent the source region;
- and
- forming an enlarged zone of an insulating layer adjacent the source region and in the removed part of the floating gate.
2 more elements
A transistor comprising:
- a substrate;
- source and drain regions in said substrate;
- a control gate above said substrate;
- a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge;
- and
- a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation.
3 more elements
A non-volatile electrically programmable memory comprising:
- a plurality of memory cells coupled to at least one word line and to at least one bit line, each memory cell comprising at least one transistor comprising
- a substrate,
- source and drain regions in said substrate,
- a control gate above said substrate,
- a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge, and
- a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation for each memory cell.
3 more elements
An electronic device comprising:
- a device comprising a plurality of memory cells coupled to at least one word line and to at least one bit line, each memory cell comprising at least one transistor comprising
- a substrate,
- source and drain regions in said substrate,
- a control gate above said substrate,
- a first zone adjacent said drain region and between said substrate and said control gate, and comprising at least one floating gate including a plurality of electrically conductive nanoparticles configured to accumulate electrical charge, and
- a second zone adjacent said source region and between said substrate and said control gate, and comprising a single insulating layer, the first zone having a thickness less than that of the second zone and configured to provide a vertical electric field that varies across the first and second zones during a transistor-programming operation for each memory cell.
3 more elements
Dependencies are inferred from the claim text.