Select Gate Formation for Nanodot Flat Cell

A memory device, comprising:

• a semiconductor channel between first and second isolation trenches;
• a tunnel dielectric layer located over the semiconductor channel;
• a memory cell stack comprising a floating gate layer comprising a plurality of electrically conductive nanodots located over the tunnel dielectric layer and a blocking dielectric layer located over the floating gate layer, wherein the memory cell stack comprises first and second substantially planar etched sidewalls on first and second opposing sides of the stack facing the first and second isolation trenches such that the edges of the floating gate layer and the blocking dielectric layer are aligned on the first and second sides of the stack;
• and
• a control gate located over the memory cell stack.

A memory device, comprising:

• a semiconductor substrate having a memory cell area and a peripheral transistor area;
• a first plurality of isolation trenches in the memory cell area, the first plurality of isolation trenches filled with a first dielectric material;
• an array of memory cells and select gate transistors located in the memory cell area between the first plurality of isolation trenches;
• a second plurality of isolation trenches in the peripheral transistor area, the second plurality of isolation trenches filled with a second dielectric material different from the first dielectric material;
• and
• a plurality of peripheral transistors located in the peripheral transistor area between the second plurality of isolation trenches.

A memory device, comprising:

• a semiconductor channel;
• a tunnel dielectric layer over the semiconductor channel;
• a plurality of memory elements over the tunnel dielectric layer, wherein each memory element comprises a floating gate layer comprising a plurality of electrically conductive nanodots located over the tunnel dielectric layer, a blocking dielectric layer located over the floating gate layer, and a charge trap layer over the blocking dielectric layer, wherein the control gates in the memory elements are separated from one another by a first spacing (SWL) between the control gates in the adjacent memory elements;
• a first select gate transistor over the tunnel dielectric layer and having second spacing (S0) between a select gate of the first select gate transistor and a control gate of the memory element adjacent to the first select gate transistor, wherein SWL<S0<2*SWL.