Vertical memory cell
AssigneeMicron Technology, Inc.
InventorsKurt D. Beigel, Sanh D. Tang
Life of this patent
Estimating the term…
Abstract
Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
Claims20
A vertical memory cell, comprising:
- a semiconductor material located between two electrodes, the semiconductor material having a plurality of doped regions and a junction between each pair of adjacent doped regions;
- and
- a gate conductor formed adjacent one of the doped regions,
- wherein a cross-sectional area of each junction is less than the cross-sectional area of the doped region having a gate conductor formed adjacent thereto.
A vertical memory cell, comprising:
- an N+ doped semiconductor cathode region formed on a cathode conductor;
- a doped P-type semiconductor P-base region formed on the N+ doped semiconductor cathode region with a first junction therebetween;
- an N-type semiconductor region formed on the doped P-type semiconductor P-base region with a second junction therebetween;
- a P+ doped semiconductor anode region formed on the N-type semiconductor region with a third junction therebetween;
- and
- at least one gate structure formed adjacent the doped P-type semiconductor P-base region, the at least one gate structure including conductive material offset from the doped P-type semiconductor P-base region by a gate dielectric,
- wherein a cross-sectional area of at least one of the first, second, or third junctions is less than the cross-sectional area of the doped P-type semiconductor P-base region.
A vertical memory cell, comprising:
- a semiconductor structure formed over a conductor line, the semiconductor structure having a first region directly below a body region, the first region including a first junction between first and second doped materials;
- and
- an etch-protective material formed on a first pair of sidewalls of the semiconductor structure above the first region;
- and
- a gate structure formed adjacent the body region, and
- wherein a cross-sectional area of the first region is smaller relative to a cross-sectional area of the body region in a first dimension.
Dependencies are inferred from the claim text.