Control gate

A semiconductor device comprising:

• a substrate;
• a split gate structure disposed on the substrate, wherein the split gate structure comprises
• a second gate disposed on the substrate;
• an inter-gate dielectric layer disposed on the substrate and over the second gate;
• a first gate, wherein the first gate is adjacent to and separated from the second gate by the inter-gate dielectric layer,
• wherein the inter-gate dielectric layer below the first gate and between the first and second gates corresponds to a charge storage layer, the first and second gates include first and second adjacent sidewalls which are adjacent to the first and second gates and first and second non-adjacent sidewalls;
• a first diffusion region adjacent to the first non-adjacent sidewall of the first gate and a second diffusion region adjacent to the second non-adjacent sidewall of the second gate;
• and
• an e-field equalizer which at least extends from the first non-adjacent sidewall to below the first gate, wherein the e-field equalizer improves uniformity of an e-field across the first gate during operation to improve charge trapping capabilities of the charge storage layer.