Nand flash memory with vertical cell stack structure and method for manufacturing same
AssigneeMosaid Technologies Incorporated
InventorHyoung Seub Rhie
Life of this patent
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Abstract
Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
Claims41
A method of manufacturing flash memory with a vertical cell stack structure, the method comprising:
- forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines, the alignment mark being formed in the substrate outside the cell area of the substrate;
- after formation of the source lines, forming cell stacking layers;
- and
- after forming the cell stacking layers, forming cell pillars in the cell stacking layers at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
A flash memory comprising:
- a substrate;
- a plurality of source lines formed in the substrate;
- a plurality of cell stacking layers formed on the substrate containing the source lines;
- a plurality of cell pillars in the cell stacking layers, each cell pillar having a pillar body, each pillar body being such that during an erase operation, the pillar body and the ion-implanted well form a single node;
- a plurality of bitlines and a plurality of wordlines, the plurality of source lines being parallel to the plurality of bitlines and comprising a respective source line for each bitline.
A method for making a flash memory device, comprising:
- forming a cell substrate in a way that a silicon surface has regions with n-type and p-type silicon;
- depositing cell stacking layers having gate material and interlayer dielectric;
- and
- patterning word lines.
A device having a vertical structure of cells and diffused source lines running in a direction perpendicular to word lines, the device comprising cell pillars and a substrate having an ion-implanted well, wherein the cell pillars are formed so that during an erase operation, each cell pillar and the ion-implanted substrate form a single node.
A method comprising:
- forming diffused source lines;
- forming a cell stack;
- performing patterning on the cell stack;
- wherein forming diffused source lines is performed before proceeding with forming the cell stack and performing patterning.
A method comprising:
- forming diffused source lines at a same photolithography mask step used to define a location of an alignment mark.
Dependencies are inferred from the claim text.