Semiconductor Device and Method of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsan-Chun Wang, Ziwei Fang
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Abstract
A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.
Claims20
A method, comprising:
- forming a NMOS gate structure over a substrate;
- forming an amorphized region in the substrate adjacent to the NMOS gate structure;
- forming a lightly doped source/drain (LDD) region in the amorphized region;
- forming a dummy spacer layer over the NMOS gate structure and the substrate after forming the amorphized region;
- patterning the dummy spacer layer to form spacers adjoining sidewalls of the NMOS gate structure;
- depositing a stress film over the NMOS gate structure;
- performing an annealing process;
- and
- removing the stress film.
(canceled)
A method of manufacturing a semiconductor device, comprising:
- forming a NMOS gate structure and a PMOS gate structure over a substrate;
- forming a protector over the PMOS gate structure;
- performing an implantation process using a silicon species to form amorphized regions in the substrate adjacent to opposite edges of the NMOS gate structure;
- forming lightly doped source/drain (LDD) regions in the amorphized regions;
- forming spacers adjoining sidewalls of the NMOS gate structure and the PMOS gate structure;
- depositing a stress film over the spacers, the NMOS gate structure, and the PMOS gate structure;
- performing an annealing process to recrystallize the amorphized regions;
- and
- removing the stress film.
(canceled)
A semiconductor device, comprising:
- a NMOS gate structure over a substrate;
- and
- a dislocation in the substrate adjacent to an edge of the NMOS gate structure, wherein the dislocation has a proximity less than about 3 nanometers and the dislocation has a depth less than about 30 nanometers.
Dependencies are inferred from the claim text.