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US 2014/0151717 A1Published application
Packaged Vertical Power Device Comprising Compressive Stress and Method of Making a Packaged Vertical Power Device
AssigneeInfineon Technologies AG
InventorRalf Otremba
Life of this patent
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Abstract
A packaged vertical semiconductive device including a compressive stress and a method of making such a packaged vertical semiconductive device are disclosed. In one embodiment an assembled device includes a carrier, a connection layer disposed on the carrier, the connection layer having a first height, and a chip disposed on the connection layer, the chip having a second height, wherein the second height is smaller than the first height.
Claims20
An assembled device comprising:
- a carrier;
- a connection layer disposed on the carrier, the connection layer comprising a first height;
- and
- a chip disposed on the connection layer, the chip comprising a second height,
- wherein the second height is smaller than the first height.
2 more elements
A packaged power device comprising:
- a leadframe;
- a connection layer disposed on a carrier;
- a vertical power semiconductor chip disposed on the connection layer, wherein the vertical power semiconductor chip comprises a compressive stress over an entire height;
- interconnects connecting chip contact pads to leads of the leadframe;
- and
- an encapsulation encapsulating the vertical power semiconductor chip.
3 more elements
A method of manufacturing a semiconductor device, the method comprising:
- placing a vertical semiconductor device with a bottom main surface on a leadframe;
- and
- connecting the semiconductor device via a connection layer to the leadframe thereby forming a compressive stress over an entire height of the semiconductor device, the connection layer being thicker than the semiconductor device.
Dependencies are inferred from the claim text.