Embedded chip package, a chip package, and a method for manufacturing an embedded chip package
AssigneeInfineon Technologies AG
InventorsEdward Fuergut, Horst Theuss, Walter Diez
Life of this patent
Estimating the term…
Abstract
An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.
Claims29
An embedded chip package comprising:
- a plurality of chips;
- encapsulation material embedding the plurality of chips;
- at least one electrical redistribution layer electrically connected to the plurality of chips;
- and
- a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.
A method for manufacturing an embedded chip package, the method comprising:
- embedding a plurality of chips in an encapsulation material;
- forming at least one electrical redistribution layer over the encapsulation material, the at least one electrical redistribution layer electrically connected to the plurality of chips;
- forming a common terminal and connecting the common terminal to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.
A chip package comprising:
- a chip comprising a sensing portion and one or more contact pads electrically connected to the sensing portion;
- and
- an electrical redistribution layer electrically contacting the at least one contact pad, wherein the electrical redistribution layer extends from the at least one contact pad to a sidewall of the chip package, wherein a portion of the electrical redistribution layer is exposed at the sidewall of the chip package.
Dependencies are inferred from the claim text.