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US 2014/0151698 A1Published application
Test Structures for Post-Passivation Interconnect
AssigneeTaiwan Semiconductor Manufactuing Company, Ltd.
InventorsHsien-Wei Chen, Jie Chen
Life of this patent
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Abstract
An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating.
Claims20
An integrated circuit structure comprising:
- a passivation layer;
- a first polymer layer over the passivation layer;
- and
- a Post-Passivation-Interconnect (PPI) monitor structure, wherein the PPI monitor structure comprises a portion overlying a portion of the first polymer layer, and wherein the PPI monitor structure is electrically floating.
1 more element
An integrated circuit structure comprising:
- a wafer comprising:
- a first chip and a second chip;
- a scribe line between the first chip and the second chip;
- a passivation layer in the wafer;
- a first polymer layer in the wafer and over the passivation layer, wherein the first polymer layer comprises:
- a first portion in the scribe line;
- and
- second portions in the first chip and the second chip, wherein the first portion is disconnected from all portions of the first polymer layer in the first and the second chips;
- and
- a first Post-Passivation-Interconnect (PPI) monitor structure comprising a portion overlying the first portion of the first polymer layer.
7 more elements
A method comprising:
- forming a passivation layer in a wafer;
- forming a first polymer layer over the passivation layer;
- forming a Post-Passivation-Interconnect (PPI) monitor structure, wherein the PPI monitor structure comprises a portion over the first polymer layer;
- and
- performing a probing to probe the PPI monitor structure, wherein a resistance between probed pads of the PPI monitor structure is measured.
2 more elements
Dependencies are inferred from the claim text.