US 2014/0151638 A1 · HYBRID NANOMESH STRUCTURES

Abstract

An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The second semiconductor material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the first semiconductor material, and the first semiconductor material is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the second semiconductor material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.

Claims25

Dependent claims

A method of forming a semiconductor structure comprising:

forming an alternating stack of a first semiconductor material and a second semiconductor material that is different from said first semiconductor material on a single crystalline substrate layer;
forming a planarization dielectric layer including a first gate cavity and a second gate cavity over said alternating stack;
forming a plurality of first semiconductor nanowires comprising said first semiconductor material underneath said first gate cavity by patterning a first portion of said alternating stack;
and
forming a plurality of second semiconductor nanowires comprising said second semiconductor material underneath said second gate cavity by patterning a second portion of said alternating stack.

2 more elements

A semiconductor structure comprising a first field effect transistor and a second field effect transistor,

wherein said first field effect transistor comprises:
a first source region comprising a first alternating stack of a first semiconductor material and a second semiconductor material that is different from said first semiconductor material;
a first drain region comprising a second alternating stack of said first semiconductor material and said second semiconductor material;
a plurality of first channels located within a plurality of first semiconductor nanowires comprising said first semiconductor material and extending between said first source region and said first drain region;
and
a first gate electrode surrounding each of said first plurality of semiconductor nanowires, and wherein said second field effect transistor comprises:
a second source region comprising a third alternating stack of said first semiconductor material and said second semiconductor material;
a second drain region comprising a fourth alternating stack of said first semiconductor material and said second semiconductor material;
a plurality of second channels located within a plurality of second semiconductor nanowires comprising said second semiconductor material and extending between said second source region and said second drain region;
and
a second gate electrode surrounding each of said second plurality of semiconductor nanowires.

8 more elements

Dependencies are inferred from the claim text.

Hybrid nanomesh structures

Life of this patent

Hybrid nanomesh structures

Life of this patent

Abstract

Claims25