Transistors and fabrication method thereof

A transistor, comprising:

• a semiconductor substrate having an isolation structure isolating different transistor regions;
• a quantum well layer on the semiconductor substrate in one transistor region;
• a potential energy barrier layer on the quantum well layer;
• a gate structure on the potential energy barrier layer;
• and
• a source and a drain on the semiconductor substrate at both sides of the gate structure connecting with the quantum well layer and the potential energy barrier layer,
• wherein:
• the gate structure is formed by sequentially:
• forming a dummy gate on a portion of the potential energy barrier layer corresponding a gate region;
• forming a sidewall spacer around the dummy gate;
• removing the dummy gate to form a first trench;
• and filling the first trench sequentially with a gate dielectric layer and a metal gate layer;
• and
• the source and the drain are formed by sequentially:
• forming trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region using the dummy gate and the sidewall spacer as a mask;
• and filling the trenches with a semiconductor material.