Method and system for high speed and low memory footprint static timing analysis

A computer-implemented method for performing static timing analysis of a circuit design comprising:

• partitioning a circuit design into a plurality of levels of gates including at least a first level of gates and a second level of gates, each of the gates in the first level having an input independent of outputs of other gates in the first level, each of the gates in the second level having an input independent of outputs of other gates in the second level;
• at a processor, performing first static timing analysis on the first level of gates responsive to loading the first level of gates into first memory of a computing device;
• storing results of the first static timing analysis into second memory of the computing device responsive to performing the static timing analysis on the first level of gates;
• and
• responsive to loading the second level of gates into the first memory, performing second static timing analysis on the second level of gates using the results of the first static timing analysis as arrival times of inputs for the second level of gates.

A non-transitory computer readable medium configured to store instructions, the instructions when executed by a processor cause the processor to:

• partition a circuit design into a plurality of levels of gates including at least a first level of gates and a second level of gates, each of the gates in the first level having an input independent of outputs of other gates in the first level, each of the gates in the second level having an input independent of outputs of other gates in the second level;
• perform a first static timing analysis on the first level of gates responsive to loading the first level of gates into first memory of a computing device;
• store results of the first static timing analysis into second memory of the computing device responsive to performing the static timing analysis on the first level of gates;
• and
• responsive to loading the second level of gates into the first memory, perform second static timing analysis on the second level of gates using the results of the first static timing analysis as arrival times of inputs for the second level of gates.

A non-transitory storage medium storing a circuit design, the circuit design generated by:

• partitioning the circuit design into a plurality of levels of gates including at least a first level of gates and a second level of gates, each of the gates in the first level having an input independent of outputs of other gates in the first level, each of the gates in the second level having an input independent of outputs of other gates in the second level;
• at a processor, performing first static timing analysis on the first level of gates responsive to loading the first level of gates into first memory of a computing device;
• storing results of the first static timing analysis into second memory of the computing device responsive to performing the static timing analysis on the first level of gates;
• and
• responsive to loading the second level of gates into the first memory, performing second static timing analysis on the second level of gates using the results of the first static timing analysis as arrival times of inputs for the second level of gates.