Efficient implementation of rsa using gpu/cpu architecture

An apparatus, comprising:

• a graphics processing unit (GPU);
• and
• a GPU compiler operative to:
• compile an inner loop body of source code;
• determine when more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations:
• peel the first iteration of the inner loop body out of the loop;
• and
• lower the type of operands in the source code.

A system, comprising:

• a central processing unit (CPU) operative to execute a main Rivest, Shamir, and Adleman (RSA) decryption function set to a value of M;
• a graphics processing unit (GPU) coupled to the CPU, the GPU operative to:
• execute GPU functions comprised of source code configured to perform RSA calculations to compute the value for M;
• and
• return the value for M to the main RSA decryption function executing on the CPU, and
• a GPU compiler operative on the GPU to:
• reduce instructions of arbitrary vector lengths into GPU supported vector lengths in an inner loop body of the source code using vector strip mining;
• and
• determine when more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations.

A method, comprising:

• passing parameters of a Rivest, Shamir, and Adleman (RSA) decryption algorithm set to a value M from a central processing unit (CPU) main function operative to be executed on a CPU to a graphics processing unit (GPU) function operative to be executed on a GPU, the GPU function comprised of source code that includes an inner loop body for calculating M;
• reducing instructions of arbitrary vector lengths into GPU supported vector lengths in an inner loop body of the source code using vector strip mining;
• re-writing the GPU function source code when more than one machine code instruction of compiled GPU function source code under-utilizes GPU instruction bandwidth limitations;
• computing a value for M on the GPU;
• and
• returning the value for M to the CPU main function.

An article of manufacture comprising a computer-readable storage medium containing instructions that when executed cause a system to:

• compile source code having an inner loop body using a graphics processing unit (GPU) compiler;
• and
• when more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations:
• peel the first iteration of the inner loop body out of the loop;
• lower the type of operands in the source code;
• and
• reduce instructions of arbitrary vector lengths into graphics processing unit (GPU) supported vector lengths in the peeled out inner loop body of a source code using vector strip mining to obtain optimized source code.