US 2013/0295740 A1 · FORMING CMOS WITH CLOSE PROXIMITY STRESSORS

Abstract

A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

Claims20

Dependent claims

A method comprising:

forming a first transistor in a first region of a substrate by forming a first gate stack on top of said first region of said substrate, said first region including a source region and a drain region of said first transistor;
forming a second transistor in a second region of said substrate by forming a second gate stack on top of said second region of said substrate, said second region including a source region and a drain region of said second transistor;
covering said first transistor with a mask, said mask does not cover said second transistor;
creating recesses in said source and drain regions of said second transistor;
and
forming stressors in said recesses.

3 more elements

A method comprising:

forming a first transistor in a first region of a substrate, said first transistor having a gate stack on top of said first region of said substrate and a set of spacers adjacent to sidewalls of said gate stack, said first region including a source region and a drain region of said first transistor;
forming a second transistor in a second region of said substrate, said second transistor having a gate stack on top of said second region of said substrate and a set of spacers adjacent to sidewalls of said gate stack, said second region including a source region and a drain region of said second transistor;
covering said first transistor with a first photo-resist mask;
creating a first set of recesses in said source and drain regions of said second transistor, said first set of recesses being self-aligned to said set of spacers of said second transistor;
forming stressors in said first set of recesses;
covering said second transistor including said stressors with a second photo-resist mask;
creating a second set of recesses in said source and drain regions of said first transistor, said second set of recesses being self-aligned to said set of spacers of said first transistor;
and
forming stressors in said second set of recesses.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/465,159Filed 7 May 2012

Published

7 Nov 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels

Forming cmos with close proximity stressors

Life of this patent

Forming cmos with close proximity stressors

Life of this patent

Abstract

Claims20