Self-repair logic for stacked memory architecture

A method comprising:

• conducting a test of a stacked memory device, the stacked memory stack including one or more memory die elements, a system element coupled with the memory stack, and a plurality of through silicon vias (TSVs);
• detecting one or more defective TSVs of the plurality of TSVs;
• and
• repairing operation of the one or more defective TSVs, the repair of operation including utilization of the one or more spare TSVs.

A system comprising:

• a processor to process data of the system;
• a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both;
• and
• a memory to store data, the memory including a stacked memory device, the stacked memory device including:
• a memory stack having one or more memory die elements, including a first memory die element, and
• a system element coupled with the memory stack, wherein the first memory die element includes:
• a plurality of through silicon vias (TSVs), the plurality of TSVs including a plurality of data TSVs and one or more spare TSVs, and
• self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair including utilization of the one or more spare TSVs.