Reducing power in sram using supply voltage control

A static random access memory (SRAM) in an integrated circuit, comprising:

• an array of memory cells arranged in rows and columns, each row of the memory cells connected to a word line, and each column of the memory cells connected to a bit line, a latch sourcing supply line and a latch sinking supply line;
• and
• a plurality of supply switches, each connected to a latch sourcing or a latch sinking supply line for one of the columns;
• wherein each memory cell in the array comprises:
• a latch connected between a latch sourcing supply line and a latch sinking supply line;
• and
• at least one read buffer;
• wherein each column of the memory cells is connected to one of the plurality of supply switches;
• wherein a first voltage is applied between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are column addressed during a read cycle of the array;
• wherein a second voltage is applied between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are not column addressed during the read cycle of the array;
• and
• wherein the first voltage is greater than the second voltage.

A static random access memory (SRAM) in an integrated circuit, comprising:

• an array of memory cells arranged in rows and columns, each row of the memory cells connected to a word line and each column of the memory cells connected to a bit line, a latch sourcing supply line, and a latch sinking supply line;
• and
• a plurality of supply switches, each connected to a latch sourcing or a latch sinking supply line for one of the columns;
• wherein each memory cell in the array comprises a latch connected between a latch sourcing supply line and a latch sinking supply line;
• wherein each column of memory cells is connected to one of the plurality of supply switches;
• wherein a first voltage is applied between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are column addressed during a read cycle of the array;
• wherein a second voltage is applied between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are not column addressed during the read cycle of the array;
• wherein the first voltage is greater than the second voltage;
• wherein a third voltage is applied between latch sourcing and latch sinking supply lines for a column of memory cells that are in the array and are column addressed during a write cycle of the array;
• wherein a fourth voltage is applied between latch sourcing and latch sinking supply lines for a column of all memory cells that are in the array and are not column addressed during the write cycle of the array;
• and
• wherein the third voltage is lower than the fourth voltage.

A supply switch in an integrated circuit, the supply switch operable to supply a voltage to an array of memory cells in the integrated circuit, the supply switch comprising:

• a first transistor having a gate operable to receive a first supply selection signal, having a source connected to a first supply voltage and having a drain connected to the array;
• a second transistor having a gate operable to receive a second supply selection signal, having a source connected to a second supply voltage and having a drain connected to the array, the second supply voltage being different from the first supply voltage;
• and
• a solid state device connected to the array and operable to supply the array with a third supply voltage that is different from each of the first and second supply voltages.