Semiconductor device having bit line hierarchically structured

Abstract

Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state.

Dependencies are inferred from the claim text.