Software and method for via spacing in a semiconductor device
AssigneeGlobalfoundries Inc.
InventorsDavid S. Doman, Mahbub Rashed, Marc Tarrabia
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AssigneeGlobalfoundries Inc.
InventorsDavid S. Doman, Mahbub Rashed, Marc Tarrabia
Estimating the term…
A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.
A method of determining the location of a plurality of power rail vias in a semiconductor device, wherein the semiconductor device includes an active region and a power rail, wherein the power rail includes the power rail vias, said method comprising:
A computer-readable software product for executing a method of determining the location of a plurality of power rail vias in a semiconductor device, wherein the semiconductor device includes an active region and a power rail, wherein the power rail includes the power rail vias, the method comprising:
A method of fabricating a semiconductor device, comprising
Dependencies are inferred from the claim text.