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US 2013/0280884 A1Published application
Methods for the Formation of a Trap Rich Layer
AssigneeIo Semiconductor, Inc.
InventorsChris Brindle, Michael A. Stuber, Stuart B. Molin
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Abstract
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
Claims30
A process for manufacturing an integrated circuit comprising:
- forming a circuit layer in a semiconductor wafer, said semiconductor wafer having a substrate and an exposed substrate surface;
- depositing a layer of polysilicon on a second semiconductor wafer;
- and
- bonding said second semiconductor wafer to an opposite surface of said semiconductor wafer, said opposite surface being on an opposite side of said semiconductor wafer from said exposed substrate surface;
- wherein said layer of polysilicon forms a trap rich layer;
- and
- wherein said trap rich layer remains in a finished structure for said integrated circuit.
4 more elements
A method comprising:
- forming an active layer in a semiconductor wafer;
- depositing a layer of high resistivity material on a handle wafer;
- and
- bonding said handle wafer to a top surface of said semiconductor wafer;
- wherein:
- said layer of high resistivity material serves as a trap rich layer for said active layer in a finished semiconductor structure;
- and
- said high resistivity material has a resistivity that is higher than or equal to a resistivity of a substrate of said handle wafer.
5 more elements
A method comprising:
- forming an active layer in a semiconductor wafer;
- implanting a stream of high energy particles into a handle wafer to create a damaged layer in said handle wafer;
- and
- bonding said handle wafer to a top surface of said semiconductor wafer;
- wherein said damaged layer serves as a trap rich layer for said active layer in a finished semiconductor structure.
2 more elements
Dependencies are inferred from the claim text.