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US 2013/0280866 A1Published application
Lead frame ball grid array with traces under die
AssigneeUTAC Thai Limited
InventorsSomchai Nondhasitthichai, Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset
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Abstract
A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.
Claims15
1-13. (canceled)
A method of making a packaged semiconductor device comprising:
- a. plating a first pattern on a top surface of a monolithic substrate thereby forming a plurality of routing traces each having a first contact point and at least one additional contact point;
- b. plating a second pattern on a bottom surface of a monolithic substrate;
- c. mounting a semiconductor die on the top surface of the monolithic substrate;
- d. electrically coupling wirebonds from the semiconductor die to first contact points of the plurality of plated routing traces;
- e. encapsulating the semiconductor die;
- f. etching away the portions of the monolithic substrate not plated by the second pattern thereby forming standoffs disposed at the at least one additional contact points;
- and
- g. singulating the semiconductor device.
5 more elements
Dependencies are inferred from the claim text.