Vertically stackable dies having chip identifier structures

A method comprising:

• a first step for forming a stack of N dies, wherein each die comprises:
• a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts;
• chip identifier selection logic coupled to the chip identifier structure;
• and
• a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one;
• and
• a second step for coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through vias has a pad that is coupled to an adjacent through via and each of the second set of the N through vias is coupled to its own respective pad.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
• a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
• and
• a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts;
• transforming the design information to comply with a file format;
• and
• generating a data file comprising the transformed design information.

A method comprising:

• receiving a data file comprising design information corresponding to a semiconductor device;
• and
• fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
• a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
• and
• a second die stacked above the first die, the second die comprising a. second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts.

A method comprising:

• receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a semiconductor structure comprising:
• a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
• and
• a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts;
• and
• transforming the design information to generate a data file.

A method comprising:

• receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board;
• and
• manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a semiconductor structure comprising:
• a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one;
• and
• a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts.

A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising:

• instructions that are executable by the computer to initiate forming a stack of N dies, wherein each die comprises:
• a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts;
• chip identifier selection logic coupled to the chip identifier structure;
• and
• a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one;
• and
• instructions that are executable by the computer to initiate coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through vias has a pad that is coupled to an adjacent through via and each of the second set of the N through vias is coupled to its own respective pad.